(a) Field of the Invention
The present invention relates to a wiring board for use in packaging an electronic component such as a semiconductor element and a method of manufacturing the same. More specifically, the invention relates to a wiring board having a structure in which multiple wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through vias formed in the insulating layers, and a method of manufacturing the same.
The aforementioned wiring board is also referred to as a “semiconductor package” in the following description for the sake of convenience, because the wiring board serves as a package for mounting a semiconductor element or the like thereon.
(b) Description of the Related Art
Heretofore, build-up process has been in wide use as a technology for manufacturing a wiring board of multilayer structure. With the use of the build-up process, the fabrication of a variety of multilayer wiring boards is possible by varying the combination of a material (typically, resin) for an inter-insulating layer and a via hole formation process. A typical manufacturing process for the multilayer wiring board using the build-up process is to stack layers on both or either of surfaces of a core substrate serving as a support base member, by repeating, in turn, formation of an insulating layer, formation of via holes in the insulating layer, and formation of a wiring layer including conductors (vias) filled in the via holes. In such a structure, wiring layers and insulating layers can be thinly formed since the build-up process is used for stacking these layers. However, a portion of the core substrate requires a thickness large enough to afford sufficient wiring board rigidity. This leads to a limitation to making a package thinner as the whole semiconductor package.
Thus, a structure without a core substrate (support base member) has been recently adopted to make a wiring board (semiconductor package) still thinner. The wiring board of such a structure is also called a “coreless board” in that the structure has no “core” portion. Although description is given later for a method of manufacturing such a coreless board, a basic process of the method includes: preparing a temporary substrate as a support; forming, in sequence, a required number of build-up layers (namely, insulating layers including via holes, and wiring layers including the insides (vias) of the via holes) on the temporary substrate; and removing the temporary substrate.
Thus, the process of fabricating a thin board (coreless board) is different form the process of fabricating a conventional thick board (board having a core) in that the support base member is eventually removed or is left as the core. Despite such a difference, the methods of forming wiring layers in these processes are basically the same. Specifically, for the coreless board, the width and pitch of a wiring pattern and the size of a wiring portion (wiring formation region) occupying the wiring board are determined under the same design rule as that for the conventional board, and the wirings are designed based on the same design rule. Thus, the distance from the board edge portion (peripheral edge of the wiring board) to the wiring portion (wiring formation region) is designed in the same manner as that for the conventional board. In the state of the art, the distance (portion where a wiring is not formed) is designed to be approximately 500 μm, for example.
An example of a technology related to the aforementioned prior art is disclosed in Japanese unexamined Patent Publication (JPP) (Kokai) 2000-323613. This publication discloses a technology to obtain a multilayer board for mounting a semiconductor device, in which a mounting surface for mounting the semiconductor device is formed as flat as possible and also as thin as possible. The multilayer board is configured of conductive wirings formed in multiple layers with insulating layers each interposed between corresponding two of the conductive wirings. Here, one surface of the multilayer board is a semiconductor element mounting surface where pads for a semiconductor element are formed, the pads being to be connected to electrode terminals of the semiconductor element to be mounted thereon. The other surface thereof is an external connection terminal bonding surface where pads for external connection terminals are formed. Further, vias electrically connecting the conductive wirings and/or the pads formed on the both surfaces of each of the aforementioned insulating layers are formed while penetrating through the insulating layer. Each of the vias is formed in a circular truncated cone like shape having an opening portion on the external connection terminal bonding surface side of a corresponding one of the insulating layers and also having a bottom surface on an inner surface side of the external connection terminal bonding surface side of the conducive wiring or the pad formed on the semiconductor element mounting surface side. Here, the area of the opening portion is larger than the area of the bottom surface.
Moreover, another example of a technology related to the aforementioned prior art is disclosed in JPP (Kokai) 2007-158174. The technology disclosed in this publication provides a method of manufacturing a coreless board. The method disclosed with individual steps involves: disposing an underlying layer in a wiring formation region on a prepreg; disposing a metal foil on the prepreg via the underlying layer in order that the metal foil larger than the underlying layer can be in contact with an outer periphery of the wiring formation region; and curing the prepreg by applying heat and pressure to the prepreg. Thereby, a temporary substrate is obtained while the metal foil is bonded to the temporary substrate. The method further involves: forming a build-up wiring layer on the metal foil; and delaminating the metal foil from the temporary substrate by cutting a peripheral edge of the underlying layer of the structure. Thereby, a wiring member including the build-up wiring layer formed on the metal foil is obtained.
As described above, the conventional coreless board (semiconductor package) is advantageous in making the board thinner because no core board is required. However, on the contrary, the rigidity of the whole package is low because the package does not include a core board. The structure is thus fragile with respect to an external mechanical stress (shock). Thus, there arises a problem in that an edge portion of a board in particular chips easily.
In other words, when a mechanical stress or shock is externally applied to the board having the structure of the conventional coreless board (semiconductor package), there is a high risk that “chipping” occurs on the edge portion of the board due to the low rigidity of the whole package. In addition, a wiring portion is exposed in some cases depending on the degree of “chipping.” Moreover, an outermost insulating layer (solder resist layer) of the package is softer than an insulating layer (build-up layer formed of an epoxy resin or the like) positioned at the inner layer side thereof, so that the outermost insulating layer may be separated from the main body of the substrate (delamination) when a mechanical stress or the like is externally applied thereto.
When the chipping or the like occurs on the board, the board is defective as a product (package). In particular, where a board edge portion chips when some kind of a mechanical stress is externally applied thereto during the manufacturing process, the board becomes a defective product at that stage as a matter of course, and also, the materials, man-hours and the like which have been spent until that stage become waste, hence resulting in a problem that the production yield is lowered.